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| ICs for Communications Memory Time Switch Large MTSL PEB 2047 PEB 2047-16 Version 2.1 Data Sheet 03.95 Edition 03.95 This edition was realized using the software system FrameMaker. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. PEB 2047 PEB 2047-16 Revision History: Previous Version: Page (in Version 01.94) 124 127 135 142 143 148 153 154 157 158 159 Page (in new Version) 5 8 16 23 25 31 36 37 40 41 42 Current Version: 03.95 Data Book 01.94 Subjects (changes since last revision) Version 2.1 Pin No. 6: INT open drain output Figure 8: Improved STAR: FSAD(2:1) position MASK: Write address Figure 12: 2 x Data Rate, Figure 13: 1 x Data Rate Abs. Max. Ratings: VS definition tLA min. = 15 ns, tAH min. = 15 ns, tRWD min. = 0 ns Figure 23: tRWD tS min. = 15 ns Sequence of 1., 2. and 3. bit of frame Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our "Product Overview". PEB 2047 PEB 2047-16 Table of Contents Page 1 1.1 1.2 1.3 1.4 2 2.1 2.2 3 3.1 3.2 3.3 3.4 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 5 6 6.1 6.2 7 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 General Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 MTSL Internal Timing and Channel Delay . . . . . . . . . . . . . . . . . . . . . . . . .15 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Operational Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Indirect Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Frame Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Mode Register (MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Status Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Interrupt Status Register (ISTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Indirect Access Register (IAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Determination of MTSL Frame Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Example for a MTSL Design guaranteeing Constant Frame Delay for all Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . .48 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Semiconductor Group 4 Memory Time Switch Large (MTSL) PEB 2047 PEB 2047-16 Preliminary Data CMOS IC 1 Features 16 384-kbit/s PCM systems q Non-blocking time/space switch for 2048-, 4096-, 8192- or q Different modes programmable for input and output separately q Configurable for a 4096-kHz, 8192-kHz or 16 384-kHz device clock q Switching of up to 1024 incoming PCM channels to up to 1024 outgoing PCM channels q 16 input and 8 output PCM lines q Tristate function for further expansion and tandem q q q q q q q q q P-LCC-44 operation P read-access to PCM data Programmable clock shift with half clock step resolution for input and output Individual line delay measurement and clock shift mechanism for 8 PCM inputs Built-in selftest 8-bit Motorola or Intel type P interface Constant or minimal channel-delay programmable on a per time-slot basis In-operation adjustment of bit-sampling without bit errors Low power consumption Single 5 V power supply Important Note: All 16 384-MHz features described in this data sheet are only available with the PEB 2047-16! Type PEB 2047-N V2.1 PEF 2047-N-16 V2.1 Ordering Code Q67100-H6238 Q67100-H6301 Package P-LCC-44 (SMD) P-LCC-44 (SMD) Semiconductor Group 5 03.95 PEB 2047 PEB 2047-16 Pin Configuration (top view) IN3 IN7 IN6 IN2 IN1 IN5 IN4 IN0 IN 8/FS0 IN 9/FS1 IN 10/FS2 7 8 9 10 11 12 13 14 15 16 17 INT IN 15/FS7 IN 11/FS3 SP ALE V SS CLK OUT2 OUT3 OUT6 OUT7 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RES OUT0 OUT1 OUT4 OUT5 AD7 AD8 AD5 AD4 AD3 AD2 PEB 2047 MTSL 18 19 20 21 22 23 24 25 26 27 28 IN 14/FS6 IN 13/FS5 IN 12/FS4 A0 CS V DD RD/DS WR/R/W AD0 AD1 A1 ITP03766 Semiconductor Group 6 PEB 2047 PEB 2047-16 1.1 Pin Definitions and Functions Symbol Input (I) Output (O) I I I I I I I I I I I I I I I I I I I I Function Ground (0 V) Synchronization Pulse: The MTSL is synchronized to the PCM system via this line. PCM-Input Ports: Serial data is received at standard TTL levels. Pin No. 1 3 14 11 10 7 13 12 9 8 15 16 17 4 20 19 18 5 21 28 VSS SP IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8/FS0 IN9/FS1 IN10/FS2 IN11/FS3 IN12/FS4 IN13/FS5 IN14/FS6 IN15/FS7 A0 A1 PCM-Input Ports or Frame (Measuring Inputs): These inputs can additionally be used as frame evaluation inputs. Address Bus Bit 0, 1: These inputs interface to the systems address bus to select an internal register for a read or write access. These pins are only active if a demultiplexed P interface mode is selected. Chip Select: A low level selects the MTSL for a register access operation. Supply Voltage: 5 V 5 %. Reset: A high signal on this input forces the MTSL into reset state. Read/Write: When "high", identifies a valid P access as a read operation. When "low", identifies a valid P access as a write operation (Motorola bus mode). Write: This signal indicates a write operation (Siemens/ Intel bus mode). Data Strobe: The rising edge marks the end of a valid read or write operation (Motorola bus mode). Read: This signal indicates a read operation (Siemens/ Intel bus mode). 22 23 39 25 CS I I I I VDD RES R/W WR 24 DS RD I I I Semiconductor Group 7 PEB 2047 PEB 2047-16 Pin Definitions and Functions (cont'd) Pin No. 26 27 29 30 31 32 33 34 38 37 43 42 36 35 41 40 44 2 Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 CLK ALE Input (I) Output (O) I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O I I Function Address Data Bus: If the multiplexed address/data Pinterface bus mode is selected these pins transfer data and addresses between the P and the MTSL. If a demultiplexed mode is used, these bits interface with the system data bus. PCM-Output Port: Serial data is sent by these lines at standard CMOS- or TTL levels. These pins can be tristated. Clock: 4096-kHz, 8192-kHz or 16 384-kHz device clock. Address Latch Enable: In the Intel type multiplexed Pinterface mode a logical high on this line indicates an address of an MTSL internal register on the external address/data bus. In the Intel type demultiplexed Pinterface mode this line is hardwired to VSS, in the demultiplexed Motorola type P-interface mode it should be connected to VDD. Interrupt Line: Active low open drain output. 6 INT (OD) Semiconductor Group 8 PEB 2047 PEB 2047-16 1.2 Logic Symbol AD (7 : 0) ALE WR RD CS A0 A1 INT IN (15 : 0) P Interface PEB 2047 PCM Interface OUT (7 : 0) VDD VSS SP CLK ITL03767 Figure 1 Functional Symbol 1.3 General Device Overview The Siemens Memory Time Switch Large MTSL (PEB 2047) is an expansion of the MTSC (PEB 2045) regarding capacity and/or functionality. It is a monolithic CMOS switching device capable of connecting maximally 1024 PCM-input time-slots to 1024 output time-slots. A constant frame delay of one frame can be selected for wideband applications (e.g. ISDN H-Channels), whereas for example for voice channels a minimal frame delay is programmable. In order to manage the problem of different line delays, eight of the PCM inputs can be used as frame measurement inputs and eight different input offsets are allowed. Thus a frame wander can be compensated by adjusting the input offset during operation. A special circuitry guarantees that no bit error will occur, when reprogramming the input offsets. The MTSL on-chip connection memory and data-memory are accessed via the 8-bit standard Pinterface (Motorola or Intel type). A built-in selftest mechanism - also activated by the P - ensures proper device operation in the system. The PEB 2047 is fabricated using the advanced CMOS technology from Siemens and is mounted in a P-LCC-44 package. Inputs and outputs are TTL-compatible. Semiconductor Group 9 PEB 2047 PEB 2047-16 1.4 System Integration The main application field for the MTSL (PEB 2047) are central switches with high switching capacity. Two possibilities exist to implement a non-blocking switch for 1024 input and 1024 output channels. With a 16 384-kHz device clock only one MTSL is needed (figure 2), with a 8192-kHz device clock two chips in parallel realize the same functionality (figure 3). PCM IN 8 MHz 8 MTSL CLK 16 8 PCM OUT 8 MHz 384 kHz ITS03768 Figure 2 Memory Time Switch for a Non-Blocking 1024-Channel Switch (16 MHz) 4 MTSL CLK PCM IN 8 MHz 8 PCM OUT 8 MHz 4 MTSL CLK 8192 kHz ITS03769 Figure 3 Memory Time Switch for a Non-Blocking 1024-Channel Switch (8 MHz) Semiconductor Group 10 PEB 2047 PEB 2047-16 Due to the tristate capability of the MTSL larger switches can be easily formed. Figure 4 and 5 show how 4 devices operating with a 16 384-kHz clock or 8 devices operating with a 8192-kHz clock can be arranged to form non-blocking 2048-channel switches. 8 MTSL PCM IN 8 MHz 8 MTSL MTSL MTSL 8 PCM OUT 8 MHz 8 ITS03770 Figure 4 Memory Time Switch for a Non-Blocking 2048-Channel Switch with Four Devices (16-MHz device clock) 4 MTSL 11 8 MTSL 12 PCM IN 8 MHz 8 MTSL 23 MTSL 13 4 MTSL 24 MTSL 14 ITS03771 MTSL 21 4 MTSL 22 PCM OUT 8 MHz 4 Figure 5 Memory Time Switch for a Non-Blocking 2048-Channel Switch with Eight Devices (8-MHz device clock) Semiconductor Group 11 PEB 2047 PEB 2047-16 2 Functional Description The MTSL is a memory time switch device. Operating with a device clock of 8192 kHz it can connect any of 1024 PCM-input channels to any of 512 output channels. With a device clock of 16 384 kHz all 1024 PCM channels can be switched to the output. Additionally a 2048-kbit/s mode with a capacity of 512 x 256 time-slots and a clock frequency of 4096 kHz is possible for systems, which need the frame integrity feature. A general block-diagram of the MTSL is shown in figure 7. The input information of a complete frame is stored in one of the two on-chip 8-Kbit data memories DM0 and DM1. The incoming 1024 channels of 8 bits each are written in sequence into fixed positions of DM0 or DM1. This is controlled by the input counter in the timing control block with a 8-kHz repetition rate. If MTSL-A1 compatible operation (i.e. no frame integrity guaranteed) is wished, only one of the two data memories is used. Otherwise DM0 and DM1 are filled alternating with input frames. For outputting, the connection memory (CM) is read in sequence. Each location in the CM points to a location in the data memory. The byte in this data memory location is transferred into the current output time-slot. The read access to the CM is controlled by an output counter. An additional bit (D12) in each location of the CM controls the access to the data memories DM0 and DM1. Three address pointers - two switching aligned to the input frame (DMI, IADP), one switching aligned to the output frame (DMO) - are working in conjunction with D12 implementing the constant/minimal delay function (see figure 6). FRAME (N-1) SP DMO FRAME N FRAME (N+1) READ TS0 from DM FRAME N DMI IADP 01 61 62 63 0 1 READ TS0 from DM FRAME N+1 READ TS0 from DM FRAME N+2 .......... .......... 63 0 .......... 63 0 WRITES TS0 to DM FRAME (N-1) WRITES TS63 to DM FRAME (N-1) WRITES TS63 to DM FRAME N ITD03772 Figure 6 Semiconductor Group 12 PEB 2047 PEB 2047-16 Constant delay (D12 = 0): Minimal delay (D12 = 1): read output time-slot from data memory (not DMO) if number of input time-slot to be switched to current output IADP then read output time-slot from data memory DMI else read output time-slot from data memory (not DMI) The synchronization of this procedure will be achieved by a rising edge of the synchron pulse SP, which is always sampled with the falling edge of the device clock. Different modes of operation are configurable at the PCM-input interface (see table 3). Furthermore, 8 PCM-input lines can be aligned with individual clock shift values to compensate different line delays. If more than 8 inputs are used one clock shift value controls up to two ports at the same time. The input lines IN8 to IN15 can be used as additional frame-measurement inputs (FS(0:7)). After synchronizing the device by the SP pulse the FS inputs can be evaluated on a per port basis. This evaluation procedure is started by a microprocessor command. As a result the input counter value on the rising edge of the FS signal can be read from an internal register. Thus delay compensation is easily managed by programming appropriate clock shift values and/or a possible software offset. During operation of the chip a frame length check is also supplied, which controls correct synchronization by the SP pulse and generates an interrupt in case of lost or achieved synchronization. The output buffer operation is controlled by mode selection and the chosen clock-rate (4096 kHz, 8192 kHz or 16 384 kHz) (see table 2). Shifting of the output frame is also possible, but all outputlines are affected the same way. The unused output ports are tristated by mode selection, whereas unused time-slots are tristated by an additional bit in the control memory. By using this tristate capability the MTSL can be easily expanded to a time switch of any size (see figure 2 to 5). Semiconductor Group 13 PEB 2047 PEB 2047-16 MOD AD0... AD7 A0...A1 ALE RD WR CS INT Timing Control Output Buffer CS Reg. CMDR STAR MASK ISTA Connection Memory CM P Interface IAR SP RES CLK OUT0 Figure 7 Block Diagram MTSL The standard 8-bit P interface can communicate with Intel multiplexed/demultiplexed microprocessors as well as with Motorola demultiplexed processors. It gives access to the internal registers and to the control- and data memory. Five directly addressable registers are provided. All other registers and the memories are accessed by a simple three byte indirect access method (similar to the MTSC PEB 2045). Semiconductor Group 14 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8/FS0 IN9/FS1 IN10/FS2 IN11/FS3 IN12/FS4 IN13/FS5 IN14/FS6 IN15/FS7 Input Buffer Data Memory DM0 DM1 OUT7 ITB03741 PEB 2047 PEB 2047-16 2.1 MTSL Internal Timing and Channel Delay Figure 7 shows the chip internal timing of writing and reading the data memory for all possible operation modes. Control Memory Reset Initialization of the device after a hardware reset (RES) is easily done with a P-command "control memory reset". After finishing this procedure all control memory channels contain the information "tristated". Evaluate Frame Measurement Signal A command and an address (0 ... 7) will be given by the P. The rising edge of the corresponding frame measurement signal (FS0 ... FS7) will be evaluated. The exact timing of the FS edge can then be read from an internal 12-bit register (resolution of a complete 8-kHz frame in half 16-MHz clock periods). MTSL-Selftest The switching path of the MTSL including input buffer, data memory, control memory, output buffer and timing control can be tested in the system by a built-in selftest. The two data memories DM0 and DM1 require two test procedures. Activating this mechanism takes (2 x 2.5) ms (4096 kHz), (2 x 1.25) ms (8192 kHz) or (2 x 0.625) ms (16 384 kHz). Finally the result "selftest ok/selftest not ok" can be read from the internal status register. After test completion the control-memory is also reset. 2.2 Special Functions The activity of all special functions can be read in the status register. Completion of these functions is indicated by interrupts. Semiconductor Group 15 PEB 2047 PEB 2047-16 Data Rate/Mbit/s x 1.024 Clock Freq./MHz x 1.024 Input 2 2 4 4 TS1 or 4 4 8 8 TS2 TS3 or 16 TS4 TS5 TS6 TS7 TS8 TS0 IN0...IN15 TS4 TS0 & TS1 IN0...IN7 TS9 TS10 TS11 TS5 TS2 TS0...TS3 IN0, IN2, IN4, IN6 Device Clock WA 4 8 W Write Data-Memory R 8 16 Read Data-Memory A WB B A OUT# 0 R TS# 2 4 TS1 OUT# 0 R TS# 4 8 TS2 TS3 6 1 R 2 R 3 1 R 3 2 R 3 3 R 3 TS2 3 R 6 0 R 7 1 R 2 R 3 R 7 4 R 3 5 R 3 6 R 3 7 R 3 Possible Read Periods 1) Possible Write Periods 1) Output A 6 6 TS4 7 7 TS5 B TS2 TS3 OUT# 0 1 2 3 4 5 6 7 RRRRRRRR TS# 55555555 TS4 TS5 - 4 - 8 OUT# 0 1 2 3 0 1 2 3 RRRRRRRR B TS4 TS5 TS6 TS# TS7 10 10 10 10 11 11 11 11 TS8 TS9 TS10 TS11 - 8 - 16 2-Mbit Mode Normal Mode * Possible read and write periods are aligned to output time-slots ITD06636 Figure 8 Data Memory Timing Semiconductor Group 16 PEB 2047 PEB 2047-16 For a system operating with 8192-kHz device clock and 8192-Mbit/s/8192 Mbit/s input/output data rate the following frame delay table can be deduced from the timing diagram: Table 1 Input Time-Slot Switched to OUT1, 2, 3 0- 2- 4- . . . 118 - 120 - 122 - 124 - 126 - 0- 2- 4- . . . 118 - 120 - 122 - 124 - 126 - 1 3 5 Switched to Output Time-Slot 6 - 127 8 - 127 10 - 127 . . . 124 - 127 126 - 127 - - - 7 - 127 9 - 127 11 - 127 . . . 125 - 127 127 - - - 0 1 0- 0- 0- . . . 0- 0- 0- 2- 4- 0- 0- 0- . . . 0- 0- 1- 3- 5- 1 1 5 7 9 - - - . . . - - - 0- 0- - - - . . . - - 0 0- 0- 2 3 119 121 123 125 127 1 3 5 123 125 127 127 127 6 8 10 1 3 Switched to OUT0 119 121 123 125 127 124 126 127 127 127 2 4 Delay/number of frames minimal delay constant delay From this table it can be seen, that it is not possible to achieve the constant delay of one frame for all switching paths. Those input time-slots, which are written to the data memory later than they should have been read (for example in the above configuration TS124 - TS127 switched to TS0 or TS1, OUT1, 2, 3), will be delayed by three frames! Semiconductor Group 17 PEB 2047 PEB 2047-16 3 3.1 Operational Description Initialization Procedure For a proper initialization of the MTSL the following procedure is recommended: First a reset pulse (RES) of at least two CLK clock-periods has to be applied. All registers contain now their reset values. In the next step the connection-memory CM is initialized by the commands CMDR:STP (1:0) = 01 (CM reset) or CMDR:STP (1:0) = 11 (MTSL selftest). After having programmed a CM-reset command, it takes 4096-clock periods until all tristate-control entries in the CM contain the value "1" (tristated). If a selftest-command was given, it takes 10 240-clock periods to achieve the same effect. Furthermore the register bit STAR:STOK (selftest o.k.) should still be set to "1" in this case, in order to prove that there is no fault on the chip. From version V2.1 up, the selftest command must be given for each data memory (DM0, DM1) separately. DM1 is tested, when register OPCR contains the reset value FFH, DM0 is tested by programming OPCR to FBH. The activity of the procedures can be monitored in STAR:PACT and an interrupt will indicate their completion. In all cases it is important, that the outputs are tristated by MOD:PSB = 0. 3.2 Operation Mode The operation mode of the device is fixed by programming MOD:OMD (1:0) and MOD:IMD (2:0) and by the device clock used at pin CLK (see table 2 and 3). 3.3 Indirect Access Register The connection-memory, data-memory and indirect registers are accessible through the indirect access register (IAR). An indirect access is performed by reading and/or writing three consecutive bytes to/from IAR. An incomplete three-byte access is indicated by STAR:Z = 1. After having read and/or written the third byte the operation selected by IAR:C (1:0), WR/RDQ is started and the bit STAR:B is set to 1. It takes at most 4.5 clock periods (8.5 clock periods for a "read data memory") until the operation is performed and STAR:B is reset. Semiconductor Group 18 PEB 2047 PEB 2047-16 3.4 Frame Evaluation Suppose the following timing at PCM input IN5 (mode 2): SP CLK FS 5 IN 5 TS 127 TS 0 ITD03773 Figure 9 If the device is in synchronized state (STAR:PSS = 1) and the command "frame evaluation at FS5" (CMDR = 58H) is programmed, the second following rising edge of FS5 is evaluated and creates the following result in register FER: D (11) =0 D (10:1) = 3E7H D (0) =0 D0 is fixed to 0 and doesn't have a meaning in 8-MHz clock operation modes. The actual offset of the incoming frame can now be calculated according to the formulas given in table 9. Semiconductor Group 19 PEB 2047 PEB 2047-16 3.5 Input Offset and Output Offset Based on the results of the frame evaluation procedures the input offsets can be adjusted by programming ICSR (7:0) corresponding to inputs IN (7:0). If data oversampling is used, the values of ICSR (7:0) can be adjusted within some limits during operation without producing bit errors: a) clockrate = 2 x datarate possible adjustment is one half clockperiod forward or backward. Data CLK ITD03774 -1 2 0 +1 2 Figure 10 b) clockrate = 4 x datarate possible adjustment is one clockperiod backward or two clockperiods forward. Data CLK ITD03775 -1 - 1 2 0 0 + 1 +1 + 3 +2 2 2 Figure 11 The output offset is the same for all output lines and is fixed in register OCSR. Semiconductor Group 20 PEB 2047 PEB 2047-16 4 4.1 Detailed Register Description Mode Register (MOD) Read/write, address: 0H Read/write, address: 0H Access in the multiplexed P-interface mode: Access in a demultiplexed P-interface mode: Reset value: 00H Bit 7 PSB PSB MD2 MD2 0 OMD1 Bit 0 OMD0 IMD2 IMD1 IMD0 PCM Stand By; a logical 0 switches the PCM-interface outputs to high impedance. If set to "1", the PEB 2047 is able to switch channels with 2048-kHz data rate, when operating with 8.192 MHz (switching capacity 512 x 512 time-slots) or 4.096 MHz (switching capacity 512 x 256 time-slots). Output Mode 1 and 0; these bits define the PCM-output mode according to the following table. OMD1 ... OMD0 Table 2 Output Modes Device Clock [kHz] 4.096 Output Mode OMD (1:0)1) 0 1 3 8.192 0 1 3 16.384 0 1 3 1) Port Numbers OUT (7:0) OUT7, OUT5, OUT3, OUT1, OUT2, OUT0 OUT (3:0) OUT (7:0) OUT7, OUT5, OUT3, OUT1, OUT2, OUT0 OUT (3:0) OUT (7:0) OUT7, OUT5, OUT3, OUT1, OUT2, OUT0 OUT (3:0) Number of Ports x Data Rate/kbit/s 8 x 2048 4 x 2048 / 2 x 4096 4 x 4096 8 x 4096 4 x 4096 / 2 x 8192 4 x 8192 8 x 8192 4 x 8192 / 2 x 16384 4 x 16384 Input and output mode combinations which use the same device clock frequency have to be selected. Semiconductor Group 21 PEB 2047 PEB 2047-16 IMD2 ... IMD0: Input Mode 2, 1 and 0; these bits define the PCM-input mode according to the following table. Table 3 Input Modes Device Clock [kHz] 4.096 MD2 1 1 1 8.192 0 0 0 1 1 1 16.384 0 0 0 0 0 1) Input Mode IMD (2:0)1) 0 1 2 0 1 2 4 5 6 4 5 6 3 7 Port Numbers IN (15:0) IN (15:12), IN (7:4) / IN (3:0) IN (7:0) IN (15:0) IN (15:12), IN (7:4) / IN (3:0) IN (7:0) IN (15:0) IN (15:12), IN (7:4) / IN (3:0) IN (7:0) IN (15:0) IN (15:12), IN (7:4) / IN (3:0) IN (7:0) IN6, IN4 / IN (3:0) IN6, IN4, IN2, IN0 Number of Ports x Data Rate/kbit/s 16 x 2048 8 x 2048 / 4 x 4096 8 x 4096 16 x 4096 8 x 4096 / 4 x 8192 8 x 8192 16 x 2048 8 x 2048 / 4 x 4096 8 x 4096 16 x 4096 8 x 4096 / 4 x 8192 8 x 8192 2 x 16384 / 4 x 8192 4 x 16984 Input and output mode cominations which use the same device clock frequency have to be selected. Semiconductor Group 22 PEB 2047 PEB 2047-16 4.2 Command Register (CMDR) Write, address 2H Write, address 1H Access in the multiplexed P-interface mode: Access in a demultiplexed P-interface mode: Address: 01H Bit 7 0 FSAD (2:0) SFE FSAD2 FSAD1 FSAD0 SFE Bit 0 RI STP1 STP0 Frame Synchronization signal Address 2 to 0; Address of the chosen FS signal 0 to 7 to be evaluated by the procedure started by SFE. Start Frame Evaluation; a one in this bit position starts the frame evaluation procedure. A read operation on register FER will stop an unfinished frame evaluation procedure. Reset Incomplete instruction; if a three byte indirect register access is not completed the internal logic must be initialized again before a new three byte access is possible. Start Procedure 1 and 0. The following procedures can be activated by these bits: RI STP0 ... STP1 Table 4 STP Commands STP1 X 0 1 STP0 0 1 1 Function No operation Start control memory reset procedure Start selftest procedure Note: Before activating one of these procedures MOD:PSB has to be set to 0. During selftest or CM reset the device will ignore the external synchronization pulse and the user has no access to the internal data memory. Semiconductor Group 23 PEB 2047 PEB 2047-16 4.3 Status Register (STAR) Read, address: 2H Read, address: 1H Access in the multiplexed P-interface mode: Access in a demultiplexed P-interface mode: Reset value: 01H Bit 7 Z Z FSAD (2:0) B PACT PSS STOK Note: FSAD2 FSAD1 FSAD0 B Bit 0 PACT PSS STOK Incomplete instruction; a three byte indirect instruction is not completed (Z = 1). Frame Synchronization signal Address 2 to 0: see CMDR. Busy; an indirect access is active (memories or indirect registers); the three byte indirect access register is not accessible. Procedure Active; one of the procedures started by the P (selftest, CM reset or frame evaluation) is active. PCM Synchronization Status; the PCM interface is synchronized (logical 1) or not synchronized (logical 0). Selftest O.K.; after a selftest procedure this bit is set to 1, if no faults are detected. This bit is only valid, if no power failure or inappropriate clocking occurred during the test (see ISTA:IR); this bit is set to 1 by a start selftest command or by hardware reset. Semiconductor Group 24 PEB 2047 PEB 2047-16 4.4 Interrupt Status Register (ISTA) Read, address: 4H Read, address: 2H Access in the multiplexed P-interface mode: Access in a demultiplexed P-interface mode: Reset value: 00H Bit 7 0 FEC PC IR 0 0 0 FEC Bit 0 PC IR PFI Frame Evaluation Completed; the indirect register FER contains a valid offset and can be read; this bit is reset by reading ISTA. Procedure Completed; the procedure started from the command register (CM reset or MTSL selftest) is finished; this bit is reset by reading ISTA. Initialization Request. The connection memory has to be programmed due to a loss of data (IR = 1). The IR bit is set after power failure or inappropriate clocking. This bit is reset by reading ISTA. It can only be retriggered again after a selftest or CM-reset procedure. PCM-Framing Interrupt; this bit being logical 1 indicates the loss or gain of synchronization. Synchronization is considered lost by the MTSL if the SP signal is not repeated within the correct period. Synchronization is considered achieved, if two consecutive SP pulses with the correct period have been received. PFI is reset by reading ISTA. Mask Register (MASK) Write, address: 4H Write, address: 2H PFI 4.5 Access in the multiplexed P-interface mode: Access in a demultiplexed P-interface mode: Reset value: 00H Bit 7 0 0 0 0 FEC Bit 0 PC IR PFI A logical 1 disables the corresponding interrupt as described in ISTA. A masked interrupt is stored internally and reported in ISTA immediately, if the mask is released. Semiconductor Group 25 PEB 2047 PEB 2047-16 4.6 Indirect Access Register (IAR) Access in the multiplexed P-interface mode: Read/write, address: 6H Access in a demultiplexed P-interface mode: Read/write, address: 3H Reset value: Only the control bits C (1:0) and WR/RDQ are initialized to 0. An indirect access is performed by reading/writing three consecutive bytes (first byte = extended control byte, second byte = data byte, third byte = address byte) to/from IAR. Bit 7 C1 C0 / D12 WR/ RDQ IA9 IA8 / D11 D10 D9 Bit 0 D8 control byte D7 D6 D5 D4 D3 D2 D1 D0 data byte IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA0 address byte C (1:0) WR/RDQ Code values to determine the type of access. If set to 1 a write access is performed; otherwise a read access is activated. Semiconductor Group 26 PEB 2047 PEB 2047-16 Table 5 Indirect Access Codes C1 0 0 0 0 1 1 1 D12 C0 0 0 1 1 0 1 1 WR/RDQ 0 1 1 0 0 0 1 Function No operation Write control memory D12 = 0 Write control memory D12 = 1 Read control memory Read data memory Read indirect register Write indirect register Max. Access Time Clock Periods - 4.5 4.5 4.5 8.5 4.5 4.5 This bit is only used as a data bit in a read or write control memory operation. Dependent on the contents of register OPCR D12 is interpreted as absolute address for data memories DM0 and DM1 (OPCR = FFH) or as a switch for constant (D12 = 0) and minimal (D12 = 1) delay (OPCR = FCH). This bit is only used as data bit in a read operation of the FER register. Data value for read/write access; if the control-memory is accessed D10 is used as a tristate control bit (0 = active, 1 = high impedance). D11 D (10:0) The incoming PCM data are transformed onto the data-memory (control memory data D12, D (10:0)) in the following way: TSN PN TSC MD Time-Slot Number Port Number Tristate Control Value (0 = active, 1 = high impedance) Minimal Delay (1 = minimal, 0 = constant frame delay), if OPCR:OC (1:0) = 00 B. Absolute address of data memories DM0, DM1 if OPCR:OC (1:0) = 11 B. Semiconductor Group 27 PEB 2047 PEB 2047-16 Table 6 Input Time-Slot Mapping Input Mode D (10:0) Valid for Inputs 0,4 D12 D10 D9 D8 D7 D6 D5 D4 MD TSC TSN D31) D2 D1 D0 IN (15:0) PN D12 D10 D9 1,5 MD MD TSC TSC TSN D12 D10 D9 TSN D4 D31) 1 D3 0 D1 D0 PN D1 PN D0 IN (15:12), IN (7:4) IN (3:0) 2,6 D12 D10 D9 MD TSC TSN D3 D2 D1 PN D0 IN (7:0) 7 D12 D10 D9 D8 D7 D6 D5 D4 MD TSC TSN (7:2) D3 D2 D1 D0* TSN0 PN / 2 TSN1 IN6, IN4, IN2, IN0 D12 D10 D9 3 MD MD TSC TSC TSN D4 TSN (7:2) D12 D10 D9 D3 D3 0 1 D1 PN D0 IN (3:0) D1 D0* IN6, IN4 TSN0 PN / 2 TSN1 1) D3 and D0 contain the inverted values in these cases. Note: D9 must be set to "0", if MOD = MD2 is set, i.e. in 2-Mbit applications. PN / 2 means, you have to multiply D (2:1) by two to generate the correct input numbers. IA9 ... IA0 Indirect Address for a read/write access If a indirect register is accessed only IA (3:0) are interpreted as address bits. Semiconductor Group 28 PEB 2047 PEB 2047-16 The control memory address is transformed to the output time-slots: Table 7 Output Time-Slot Mapping Output Mode Valid for Outputs 0 IA9 IA8 TSN IA3 IA2 IA1 PN IA0 OUT (7:0) IA9 1 IA9 IA8 TSN IA8 TSN IA3 IA2 IA2 IA1 PN IA1 PN 1 0 OUT7, OUT5, OUT3, OUT1 OUT2, OUT0 3 IA9 IA8 TSN IA2 IA1 IA0 PN OUT (3:0) Note: IA9 is only valid within applications with a 16.384-MHz device clock. If a 8.192 or 4.096-MHz clock is used, it is internally fixed to 0. IA8 must be set to "0", if MOD:MD2 is set, i.e. in 2-Mbit applications. Semiconductor Group 29 PEB 2047 PEB 2047-16 4.7 Indirect Registers Input Clock Shift Registers ICSR (7:0) Read/write at indirect address IA (3:0) = 0H ... 7H Reset value: 40H Bit 0 1 ICS4 ICS3 ICS2 ICS1 ICS0 RRE Bit 7 ADSR ADSR ICS4 ... ICS0 Add Shift Register; a three bit shift register is inserted into the corresponding input(s). Input Clock Shift; the value of ICS (4:0) determines the number of clock cycles by which the bit sampling point is shifted forward in all input modes. Note: ICS4 has to be set to "0" in input modes 0, 1 and 2. RRE Receive on Rising Edge These eight registers determine the individual clock shift of inputs IN0 to IN7. If more than eight inputs are used, two inputs are controlled by one ICSR register: ICSR0 ICSR1 ICSR2 . . . ICSR7 " controls " " IN0, IN8 IN1, IN9 IN2, IN10 . . . IN7, IN15 Semiconductor Group 30 PEB 2047 PEB 2047-16 Input Timing ICS (4 : 0) RRE SP CLK TS 0, Bit 7 TS 0, Bit 6 TS 0, Bit 7 TS 0, Bit 7 IN# IN# IN# 00 H 00 H 02 H 0 1 0 Figure 12 Device Clock = 2 x Data Rate ICS (4 : 0) SP CLK TS 0, Bit 7 Bit 6 Bit 6 TS 0, Bit 7 TS 0, Bit 7 RRE IN# IN# IN# 00 H 00 H 01 H 0 1 0 ITD03777 Figure 13 Device Clock = Data Rate Semiconductor Group 31 PEB 2047 PEB 2047-16 ICS (4 : 0) RRE SP CLK TS 0, Bit 7 TS 0, Bit 7 TS 0, Bit 7 IN# IN# IN# 00 H 00 H 04 H 0 1 0 ITD03778 Figure 14 Device Clock = 4 x Data Rate Operation Control Register (OPCR) Read/write at indirect address IA (3:0) = DH Reset value: FFH Bit 0 1 1 1 1 SDM OC1 OC0 Bit 7 1 SDM OC (1:0) Select Data Memory; only used in configuration with OC (1:0) = 11B Operation Control; OC (1:0) determine the usage of the two data memory blocks according to the table below. Table 8 OC1 1 0 0 1 OC0 1 0 1 0 Function Only one data memory block is used; the absolute address is given by SDM; bit D12 in the control memory is also interpreted as absolute address. Both data memory blocks are used; bit D12 in the control memory controls the constant or minimal frame delay function. Reserved Reserved Semiconductor Group 32 PEB 2047 PEB 2047-16 Output Clock Shift Register (OSCR) Read/write at indirect address IA (3:0) = EH Reset value: 20H This register determines the clock shift for all outputs. Bit 7 VN2 OCS (3:0) XFE VN1 VN0 OCS3 OCS2 OCS1 OCS0 Bit 0 XFE Output Clock Shift Transmit on Falling Edge OCSR (3: 0) XFE SP CLK TS0, Bit7 TS0, Bit6 Device Clock = 2 x Data Rate TS0, Bit7 TS0, Bit6 TS0, Bit7 TS0, Bit6 TS0, Bit7 0H TS0, Bit7 Device Clock = Data Rate TS0, Bit7 1H 0 ITD03779 0H 0H 1H 0 1 0 0 1 0H Figure 15 Output Timing and Clock Shift Semiconductor Group 33 PEB 2047 PEB 2047-16 VN (2:0) Version Number according to the table below: Table 9 Version Number VN2 0 0 VN1 0 0 VN0 0 1 Device Versions A1 V2.1 (B1) Frame Evaluation Register (FER) Read at indirect address IA (3:0) = FH Reset value = XXX After a frame evaluation procedure this 12-bit register contains the input counter offset between the SP frame and an evaluated FS0 ... FS7 frame. The evaluation is performed at the second following rising edge of FS after the command CMDR:SFE = 1 was programmed. Bit 7 D11 D7 D11 D (10:0) D6 D5 D4 D3 D10 D2 D9 D1 Bit 0 D8 D0 The FS-rising edge was sampled during the clock-high phase (D11 = 1), or during the clock-low phase (D11 = 0). The FS-rising edge was sampled at: input counter value + 1 if D11 = 1 input counter value + 2 if D11 = 0 With a device clock of 8 MHz D0 is fixed to 0 and D (10:1) contain the input counter value. The actual offset between the SP frame and an evaluated FS frame can be calculated by the following formulas: CLK x 1.024 MHz 8 Offset Value/Number of Clock Periods (D (10:1)H + 01DH)MOD1024 (D (10:1)H + 01EH)MOD1024 16 (D (10:0)H + 03DH)MOD2048 (D (10:0)H + 03EH)MOD2048 4 (D (9:1)H + 01DH)MOD512 (D (9:1)H + 01EH)MOD512 D11 0 1 0 1 0 1 FS-Rising Edge at CLK low CLK high CLK low CLK high CLK low CLK high Semiconductor Group 34 PEB 2047 PEB 2047-16 Definition of the calculated offset value: SP CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 . . ITD03780 Figure 16 Formulas for Offset Calculation Note: The device must be synchronized to SP (STAR: PSS = 1) in order to generate a correct result in FER. Semiconductor Group 35 PEB 2047 PEB 2047-16 5 Electrical Characteristics Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage at any pin with respect to ground Maximum voltage on any pin Symbol Limit Values 0 to 70 - 65 to 125 - 0.4 to VDD + 0.4 7 Unit C C V V TA Tstg VS Vmax Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Characteristics Ambient temperature under bias range; VDD = 5 V 5 %, VSS = 0 V. Parameter L-input voltage H-input voltage L-output voltage H-output voltage H-output voltage Symbol Limit Values min. max. 0.8 0.45 2.4 V V V V 20 34 10 10 mA mA A A - 0.4 2.2 Unit Test Condition VIL VIH VOL VOH VOH VDD + 0.4 V IOL = 2 mA IOH = - 400 A IOH = - 100 A VDD = 5 V, inputs at 0 V or VDD, no output loads 0 V < VIN < VDD to 0 V 0 V < VOUT < VDD to 0 V VDD - 0.5 Operational power supply current fCLK = 8192 kHz ICC fCLK = 16384 kHz ICC Input leakage current Output leakage current ILI ILO Capacitances TA = 25 C, VDD = 5 V 5 %, VSS = 0 V. Parameter Input capacitance Output capacitance I/O capacitance Symbol min. Limit Values max. 10 15 20 pF pF pF Unit CIN COUT CIO Semiconductor Group 36 PEB 2047 PEB 2047-16 AC Characteristics Ambient temperature under bias range, VDD = 5 V 5 %. Inputs are driven at 2.4 V for a logical 1 and at 0.4 V for a logical 0. Timing measurements are made at 2.0 V for a logical 1 and at 0.8 V for a logical 0. The AC testing input/output waveforms are shown below. 2.0 Test Points 0.8 2.0 0.8 Device Under Test C Load = 150 pf ITS00568 Figure 17 I/O Waveform for AC Tests P-Interface Timing Parameters Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address setup time to WR, RD Address hold time from WR, RD RD delay after WR setup RD pulse width Data output delay from RD Data float from RD RD control interval WR pulse width Data setup time to WR + CS Data hold time from WR + CS WR control interval R/W delay after RD setup Symbol min. Limit Values max. ns ns ns ns ns ns ns ns 100 25 70 60 30 10 70 0 ns ns ns ns ns ns ns ns 30 10 15 0 10 15 0 120 Unit tAA tAL tLA tAS tAH tDSD tRR tRD tDF tRI tWW tDW tWD tWI tRWD Address latch setup time to WR, RD tALS Semiconductor Group 37 PEB 2047 PEB 2047-16 t RR RD x CS t RI t DF t RD AD0 - AD7 Data ITT00712 Figure 18 P-Read Cycle t WW WR x CS t WI t WD t DW AD0 -AD7 Data ITT00713 Figure 19 P-Write Cycle Semiconductor Group 38 PEB 2047 PEB 2047-16 t AA ALE t AD WR x CS or RD x CS t ALS t AL t LA Address ITT00714 AD0 - AD7 Figure 20 Multiplexed Address Timing WR x CS or RD x CS t AS A0 - A5 Address t AH ITT00715 Figure 21 Demultiplexed Address Timing Semiconductor Group 39 PEB 2047 PEB 2047-16 Motorola Bus Mode R/W t DSD t RR t RWD t RI CS x DS t DF t RD D0 - D7 Data ITT00716 Figure 22 P-Read Cycle R/W t DSD t WW CS x DS t RWD t WI t WD t DW AD0 - AD7 Data ITT00717 Figure 23 P-Write Cycle CS x DS t AS AD0 - AD5 t AH ITT00718 Figure 24 Address Timing Semiconductor Group 40 PEB 2047 PEB 2047-16 PCM-Interface Characteristics Parameter Clock period Clock period low Clock period high Clock period Clock period low Clock period high Frame setup time Frame hold time Serial data input setup time Serial data input hold time Serial data input setup time Serial data input hold time PCM-serial data output delay time Symbol min. Limit Values max. ns ns ns ns ns ns ns ns ns ns ns ns 30 ns PCM-input data frequency 16496 kHz only PEB 2047-16 PCM-input data frequency 8192 kHz PEB 2047 120 50 50 60 27 23 15 20 15 20 15 20 Unit Condition tCP tCPL tCPH tCP tCPL tCPH tFS tFH tS tH tS tH tD PEB 2047-16 Semiconductor Group 41 PEB 2047 PEB 2047-16 t CP t CPH t CPL CLK t FH t FS SP t FH t FS tD OUT (OSCR:XFE = 0) 1st Bit of Frame 2nd Bit of Frame tS Clock Rate = 4 x Data Rate tH 3rd Bit of Frame 1st Bit of Frame 2nd Bit of Frame IN (ISCR:RRE = 0) OUT (OSCR:XFE = 1) 1st Bit of Frame 2nd Bit of Frame tD tS IN (ICSR:RRE = 1) OUT (OCSR:XFE = 0) 1st Bit of Frame tD 2nd Bit of Frame 3rd Bit of Frame tH 1st Bit of Frame tS Clock Rate = 2 x Data Rate tH IN (OCSR:RRE = 0) 1st Bit of Frame tD OUT (OCSR:XFE = 1) 1st Bit of Frame tS IN (ICSR:RRE = 1) tH 1st Bit of Frame ITD03781 Figure 25 AC Characteristics at the PCM Interface Semiconductor Group 42 PEB 2047 PEB 2047-16 t CP t CPH t CPL CLK t FH t FS t FS t FH SP tH tS IN (ICSR:RRE = 0) 1st Bit of Frame Clock Rate = 4 x Data Rate tH tS IN (ICSR:RRE=1) 1st Bit of Frame ITD03782 Figure 26 AC Characteristics at the PCM Interface Semiconductor Group 43 PEB 2047 PEB 2047-16 6 6.1 Applications Determination of MTSL Frame Delay When switching time slots from the input of the MTSL to its output, the question often arises whether the incoming channel is transmitted in the same frame (0 frame delay), the next frame (1 frame delay), or even in the frame thereafter (2 frames delay). Because framing delay is different depending on the selected output port, delay timings have to be calculated separately for all outputs. The following text advises how to do this calculation and delivers a value for MINIMAL or CONSTANT delay. A CONSTANT delay may be programmed by the control byte bit D12 of IARregister. Instructions for Use 1. Determine the data rate for the input data stream and for the output data stream. e.g. 4 Mbit/s for input data stream; 4 Mbit/s for output data stream. 2. Select a device clock. Please note, that not all ouput ports are available for every choice of the device clock (refer to the following table) !! e.g. 8 MHz. 3. Determine the constant Td for your special configuration by selecting the corresponding row in the table below (a, b, c or d): e.g. for a 4 Mbit/s input- /output- data stream with 8 MHz device clock row a) has to be selected. The table delivers a value Td = 4 for line OUT0 and Td = 3 for OUT1 ... 7. A big value for Td also means a big internal switching delay. Input Data Output Data Device Rate [Mbit/s] Rate [Mbit/s] CLK [MHz] a) b) c) d) 2, 41) 4, 8 2, 41) 4, 8 2 4, 8, 16 2, 41) 4, 8, 16 2 4 4 8 4 8 8 16 4 8 4 8 8 16 8 16 Td for OUT0 4 7 6 11 Td for OUT1 3 6 5 10 Td for Td for OUT2 ... 3 OUT4 ... 7 3 6 5 10 3 not available !! 5 not available !! 1) 2, 4 has the meaning 2,048 Mbit/s or 4,096 Mbit/s Semiconductor Group 44 PEB 2047 PEB 2047-16 4. Determine the constant M. The value for M can be determined by selecting the corresponding row in the table below (a, b or c) for your configuration. e.g. for a 4 Mbit/s input- /output- data stream with 8 MHz device clock row a) has to be selected. The table delivers the value M = 1. The Constant M for Different Data Rates... Input Data Rate [Mbit/s] a) b) 2, 4 4, 8 2, 4 4, 8 2 4, 8, 16 2, 4 4, 8, 16 Output Data Rate [Mbit/s] 2 4 4 8 4 8 8 16 Device CLK [MHz] 4 8 4 8 8 16 8 16 M 1 2 c) 4 5. Determine the constant K. The value for K can be determined by selecting the corresponding row in the table below (a, b or c) for your configuration. e.g. for a 4 Mbit/s input- /output- data stream with 8 MHz device clock row a) has to be selected and the table delivers the value K = 1. Input Data Rate [Mbit/s] a) 2 2 4 4 4 8 8 16 Output Data Rate [Mbit/s] 2, 4 4, 8 4, 8 8, 16 2, 4 4, 8 8, 16 8, 16 Device CLK [MHz] 4 8 8 16 4 8 16 16 Number of Input TS [K] Sampled at the same Time 1 b) 2 c) 4 Semiconductor Group 45 PEB 2047 PEB 2047-16 6. By inserting the obtained values for K, M and Td in the table below, minimal and constant frame delays may be calculated for every timeslot (TS). Input TS Minimal Delay = 0 Frame for Output TS Td + (0 x M) ... maxo Td + (1 x M) ... maxo Td + (2 x M) ... maxo Td + (3 x M) ... maxo ... . maxo + 1 - (n + 1) x M + Td ... maxo - Minimal Delay = 1 frame for Output TS 0 ... (Td - 1 + 0 x M) 0 ... (Td - 1 + 1 x M) 0 ... (Td - 1 + 2 x M) 0 ... (Td - 1 + 3 x M) ... . 0 ... maxo - (n + 1) x M + Td Td - n x M ... maxo . . Td - 2 x M ... maxo Td - 1 x M ... maxo 1 1 Minimal Delay = 2 Frames for Output TS - 0 x K ... (1 x K - 1) 1 x K ... (2 x K - 1) 2 x K ... (3 x K - 1) 3 x K ... (4 x K - 1) . . maxi + 1 - (n + 1) x K ... maxi-n x K maxi + 1 - n x K ... maxi - (n - 1) x K . . maxi + 1 - 2 x K ... maxi-1 x K maxi + 1 - 1 x K ... maxi-0 x K constant delay in [frames] 0 ... (Td - n x M - 1) . . 0 ... (Td - 2 x M - 1) 0 ... (Td - 1 x M - 1) 3 The other constants inserted are: n: maxi: maxo: This constant is a max. counter value that is obtained by integer division of Td by M. Is the maximal number of input time slots - 1 Is the maximal number of output time slots - 1 Please note: A negative value means no entry in the table! Example The example below will demonstrate the usage for a system with 8 MHz device CLK and 4 Mbit/s input and output data streams. Before starting the calculation the value n must be found by integer division of Td by M. With the values Td = 4 and M = 1 the value for n = 4. With Td = 3 and M = 1 the value for n = 3. The maximal number of input time slots : maxi = 64 - 1 = 63 The maximal number of output time slots: maxo = 64 - 1 = 63 Semiconductor Group 46 PEB 2047 PEB 2047-16 Frame Delay for OUT0 with Td = 4, K = 1, M = 1, n = 4, maxo = 63, maxi = 63: Input TS Minimal Delay = 0 frame for Output TS 4 ... 63 5 ... 63 6 ... 63 . . 63 - Mminimal Delay = 1 Frame for Output TS 0...3 0...4 0...5 . . 0 ... 62 0 ... 63 1 ... 63 2 ... 63 3 ... 63 1 Minimal Delay = 2 Frames for Output TS - 0 1 2 . . 59 60 61 62 63 constant delay in [frames] - 0 0...1 0...2 3 1 Frame Delay for OUT1 ... 7 with Td = 3, K = 1, M = 1, n = 4, maxo = 63, maxi = 63: Input TS Minimal Delay = 0 frame for Output TS 3 ... 63 4 ... 63 5 ... 63 . 63 - Minimal Delay = 1 Frame for Output TS 0...2 0...3 0...4 . . 0 ... 62 0 ... 63 1 ... 63 2 ... 63 1 Minimal Delay = 2 Frames for Output TS - 0 1 2 . . 60 61 62 63 constant delay in [frames] -0 0 0...1 3 1 Semiconductor Group 47 PEB 2047 PEB 2047-16 6.2 Example for a MTSL Design guaranteeing Constant Frame Delay for all Time Slots In order to achieve a constant frame delay of all PCM channels switched from input to output, the following work-around is suggested. The device is operated with a 16-MHz clock and 8 x 8 MHz PCM lives for input and output respectively. The effective switch capacity is reduced to 512 x 512. IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 MTSL Figure 27 MTSL Operation Mode with Constant Frame Delay (frame delay = 1) The general idea in this configuration is to switch all input time-slots, which would be passed to the output in the same frame (input TS# + OFFSET < output TS#), to OUT [4:7] followed by a switch from IN [4:7] to the desired output time-slot at OUT [0:3]. Thus a constant frame delay of one frame can be achieved (refer to table 10). Semiconductor Group 48 PEB 2047 PEB 2047-16 For a 8 MHz/8 MHz-system for example the following frame delay table can be deduced from the timing diagram: Table 10 Frame Delay Input Time-Slot IN0 ... IN4 or 0- 2- 4- . . . 118 - 120 - 122 - 124 - 126 - 1 3 5 Switched to Output Time-Slot 6 - 127 8 - 127 10 - 127 . . . 124 - 125 126 - 127 - - - 7 - 127 9 - 127 11 - 127 . . . 127 - - - - 0 0- 0- 0- . . . 0- 0- 0- 2- 4- 0- 0- 0- . . . 0- 0- 1- 3- 5- 1 5 7 9 - - . - . . . - - - 0- 0- - - - . . . - . - 0 0- 0- 2 (IN4 ... IN7 switched to OUT1 ... OUT3) 119 121 123 125 127 123 125 127 127 127 6 8 10 1 3 IN4 ... IN7 switched to OUT0 0- 1 2- 3 4- 5 . . . 120 121 122 - 123 124 - 125 126 - 127 126 127 127 127 127 2 4 Delay/Number of frames Semiconductor Group 49 PEB 2047 PEB 2047-16 7 Package Outlines Plastic Package, P-LCC-44 (SMD) (Plastic Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Dimensions in mm Semiconductor Group 50 GPL05102 |
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